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DS1678 Real-Time Event Recorder
24 of 25
Figure 6. Data Transfer on I
2C Serial Bus
MSB
slave address
R/W
direction
bit
SDA
SCL
START
CONDITION
12
6
78
9
12
8
9
STOP CONDITION
OR
REPEATED
START CONDITION
3 - 8
acknowledgement
signal from receiver
acknowledgement
signal from receiver
ACK
repeated if more bytes
are transferred
Figure 7. I
2C Serial Communication with DS1678
A2
10
W
0
A
0W
1
S
1
0
A1
A0
00
A
P
SD A
SC L
D e vic e A d dres s B y te
M em ory A ddress B yte
Sta rt
D S 1678
AC K
Sto p
D S 1678
ACK
W rite to M em o ry A d d ress P o in ter
1
S
1
0
00
Rd
A
N
P
SD A
SC L
D e v ice A d d res s B y te
D a ta B yte
Sta rt
D S 1678
AC K
Sto p
Ma s te r
NA CK
R ead S in g le B yte fro m C u rre n t M em o ry A d d re ss P o in ter L o catio n
D1
D2
D3
D4
D5
D6
D7
0
D0
1
S
1
0
D0
00
Rd
A
SD A
SC L
D e v ice A d d res s B y te
M os t S ignificant
D a ta B yte
Sta rt
D S 1678
AC K
Ma s te r
AC K
R ead M u ltip le B ytes fro m C u rren t M em o ry A d d ress P o in ter L o catio n
D1
D2
D3
D4
D5
D6
D7
NP
Sto p
Ma s te r
NA CK
Leas t S ignific ant
D a ta B yte
D1
D2
D3
D4
D5
D6
D7
0
D0
1
S
1
0
00
A
SD A
SC L
D e v ice A d d res s B y te
M e m o ry A d dres s B y te
Sta rt
D S 1678
AC K
D S 16 78
AC K
R ead S in g le B yte fro m N ew M em o ry A d d ress P o in te r L o catio n
1
R
1
0
00
Rd
A
D e v ice A ddress
By te
R epeated
Sta rt
D S 1678
AC K
NP
D a ta B yte
S to p
Ma s te r
NA CK
D1
D2
D3
D4
D5
D6
D0
SD A
SC L
D7
SD A
SC L
W rite to M e m ory Lo c a tion (S ingle B y te )
AP
Sto p
D S 1 678
AC K
D0
D a ta B yte
D1
D2
D3
D4
D5
D6
D7
A3
A4
A5
A6
A7
0W
1
S
1
0
A1
A0
00
A
D e v ice A ddress B yte
M e m o ry A ddres s B y te
Sta rt
D S 1 678
AC K
D S 1678
AC K
A2
A3
A4
A5
A6
A7
1
A1
A0
A2
A3
A4
A5
A6
A7
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